1. Technical Field
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Related Art
Recently, in advanced device development for miniaturization after 32 nm node generation, it is anticipated that a high-dielectric constant (high-k) gate insulating film/metal gate (HK/MG) process technique will be put into practical use. In addition, there is known a technique, in which a memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM) and a logic circuit such as a complementary metal oxide semiconductor (CMOS) are integrated on the same substrate. When the memory and the logic circuit are integrated using the HK/MG process, it is problematic that allowable limits of the leakage currents in each region are different.
Japanese Laid-open Patent Publication No. 2002-110816 discloses a technique in which the metal gate structure is adapted to a cell transistor, and a gate structure obtained by stacking poly-silicon and metal is adapted to the peripheral circuit. As a result, this document describes that the N-type transistor of the peripheral circuit controls the threshold voltage based on the N-type dopant density doped in the poly-silicon, the dielectric constant and the thickness of the gate insulating film, and the P-type dopant density in the silicon crystal region, and the cell transistor controls the threshold voltage based on a work function of metal, the dielectric constant and the thickness of the gate insulating film, and the p-type dopant in the silicon crystal region. In addition, it is anticipated that the read or write speed of the DRAM memory can be improved.
In addition to the embedded memory technique, there is known a technique of a CMOS circuit, in which a metal (oxide) layer (metal cap film) is inserted between the metal gate electrode and the gate insulating film to adjust the threshold voltages of NMOSFET and CMOSFET (refer to Japanese Laid-open Patent Publication Nos. 2007-134456 and 2008-537359, and S. Kubiceketal, 2008, Symposium on VLSI Technology Digest of Technical Papers, pp. 130-131.